FPGA Design Engineer ( Chandler, AZ ) 1370512+ Month Contract

 

Pay Rate: Open for the right candidate

 

US Citizenship Required

 

FPGA Design Engineers to be involved in full life-cycle product development of launch vehicle avionics and test system design.

In this role, you will identify, investigate, design, and develop programmable logic solutions, in FPGAs or CPLDs, for digital electronic equipment using VHSIC Hardware Description Language (VHDL) to solve a variety of technical challenges. You will test programmable logic designs in the lab using custom and/or industry standard tools and equipment to analyze performance and verify functionality meets established design requirements.

 

This position is for either a Principal Engineer or Senior Principal Engineer Digital:

 

Basic Qualifications for Principal Engineer Digital:• B.S. degree in Electrical Engineering (Computer or Electrical), or related field with a minimum of 5 years of relevant professional work experience OR a M.S. degree with a minimum of 3 years of relevant professional work experience in EE/CE including experience in programmable logic design.• Recent experience with Hardware Description Language (VHDL) and formal verification (OSVVM preferred) for FPGAs, CPLDs and/or ASICs.• Ability to work in teams and communicate clearly across various levels of engineers• Ability to translate system performance and operational specifications into programmable logic requirements, design specifications, test specifications, and users’ guides.• US Citizenship with the ability to obtain and maintain a Security Clearance

 

Preferred Qualifications:• Experience with Electronic Design Automation (EDA) Tools: Mentor Graphics ModelSim/QuestaSim, Radiant (Lattice), Vivado/ISE (Xilinx), Libero (Microsemi)

Preferred candidate will have familiarity with:• Communication protocols (UART, SPI, I2C, 1-Wire, Ethernet, AXI, APB, SpaceWire);• Fixed-point math fundamentals;• Static timing analysis and timing closure (setup and hold, slack, skew, etc.);• Asynchronous clock domain crossing and general metastability mitigation techniques;• Test-bench development, including timing-accurate bus functional models, complete functional coverage, etc.• Working in an Agile project format, team-based environment, including Jira and Git environments.• Formal verification with OSVVM