Experience:

• 10+ years of relevant front-end digital ASIC design experience, encompassing the entire flow from RTL design to synthesis.
• Minimum 5 years of experience in designing complex System-on-Chip (SoC) architectures.
• In-depth understanding of multi-CPU subsystem architecture, cache coherency protocols, and memory hierarchies.
• Solid understanding of SoC system-level architectures.
• Experience with CPU integration, bus fabrics, and DDR interfaces.
• Familiarity with the ARM ecosystem, including CPUs, GPUs, and other components.

Technical Skills:

• Proven experience with RTL synthesis tools (e.g., DC, DC-topo, RTLA, Fusion Compiler).

Soft Skills:

• Customer-focused with a strong desire to collaborate and find solutions.
• Experience working directly with customers or alongside a sales team.
• Highly motivated, with excellent problem-solving and results-driven approach.
• Strong presentation and organizational skills.
• Passionate about mentoring and guiding others through complex challenges.
• Team player with the ability to take initiative.

Travel:

• Approximately 10% travel within North America (USA and Canada) required.