Reporting to the Director Packaging Design you will be a key senior technical contributor on a high-skill, multi-site, cross-functional team pushing the envelope in customer driven high-speed SoC packaging design. You will own the package designs, as well as all processes from beginning to end. Strong presentation and communication skills. Great opportunity to move up the technical ladder.

You will have a broad knowledge of semiconductor packaging design, modeling, extraction, and simulations. Substrate design focus on signal and power integrities analyses, as well as routing analyses. High performance build-up substrates, flip chip assembly or 2.5D packaging. Extracting - simulating package designs for Signal and Power integrities using tools such as HFSS and-or ADS.

Title: Engineer 

Location:  San Jose, CA. Hybrid onsite 2-3 days weekly. Full relocation offered.

Compensation: The base salary is open. We are seeing a range ~$220,000 as competitive given the overall package. Also offered: a bonus plan and generous employer contributions to healthcare, 401(k), Holidays, PTO, etc.

Highly desirable:

~ PhD/MS with

~ Applications that included high speed Serdes 112, PCIeX5, PCIeX6, LPDDR4, LPDDR5, Ethernet 25.

~ PDN model time and frequency, Impedance profile, AC drop, etc.

~ Package HSPICE and RLC model extraction and designs

~ GHZ s-parameters extraction and verification

~ Chip and package Reliability analyses

~ BER analyses of high speed signaling

~ Dielectric loss and dielectric constant

~ Multi-physics electro-thermal analysis

~ Power-Aware SI/PI analysis

Highly skilled H1B and TN visa are encouraged to apply.