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Hybrid
Compensation:
$80 - $90 / hr
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This role requires candidates who are currently authorized to work in the U.S. without sponsorship, and C2C arrangements are not accepted. This role is on-site and then hybrid in Aliso Viejo, CA.
Job Summary:
We are seeking an experienced ATE Test Engineer Consultant to enhance existing wafer test solutions, implement advanced trimming techniques, and lead the transition from multi-site wafer testing to single-site final test setups. Work will be performed on the Advantest 93K SmartScale/ExaScale platform.
Responsibilities
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Transition multi-site wafer test configurations to single-site final test setups.
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Develop and update test programs based on new requirements and production needs.
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Collaborate with cross-functional teams to integrate Design-for-Test (DfX) into new products.
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Analyze debug results, recommend improvements, and optimize test coverage.
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Create and simulate digital/analog test patterns and generate tester-specific vectors.
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Define new test methods and develop production/characterization hardware.
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Analyze test data, prepare reports, and support mass production releases.
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Serve as primary contact for failure analysis and troubleshooting.
Qualifications
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Bachelor’s degree in Electrical Engineering or Computer Science (or equivalent).
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10+ years of ATE test engineering experience; familiarity with V93000 SOC Tester SMT8 preferred.
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Strong analytical, programming, and problem-solving skills.
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Proficiency in scripting (Perl, Python) and high-level languages (C/C++, Java).
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Experience in post-silicon validation, debug, and product engineering.
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Knowledge of load board design, testing, and debugging.
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RF, SOC, and MIPI protocol experience a plus.
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